The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Nov. 19, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yuichiro Suzuki, Yokohama, JP;

Noboru Ooike, Yokohama, JP;

Masashi Yoshida, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/12 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 11/5628 (2013.01); G11C 16/12 (2013.01);
Abstract

According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.


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