The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Feb. 27, 2017
Applicant:

Toshiba Memory Corporation, Minato-Ku, Tokyo, JP;

Inventors:

Shinya Koizumi, Kamakura Kanagawa, JP;

Kiyotaka Iwasaki, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G11C 16/08 (2006.01); H03M 13/35 (2006.01); G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 29/04 (2006.01); H03M 13/15 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G06F 11/1076 (2013.01); H03M 13/356 (2013.01); H03M 13/611 (2013.01); G11C 11/5621 (2013.01); G11C 16/0483 (2013.01); G11C 2029/0411 (2013.01); H03M 13/1102 (2013.01); H03M 13/152 (2013.01); H03M 13/1515 (2013.01);
Abstract

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.


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