The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Jan. 28, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Hiroki Date, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); G11C 16/28 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 16/10 (2006.01); H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 27/11526 (2017.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/28 (2013.01); G11C 16/32 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01);
Abstract

A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.


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