The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Feb. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Junji Koyama, Yokohama Kanagawa, JP;

Kenji Ichihara, Kawasaki Kanagawa, JP;

Keizo Ikeda, Yokohama Kanagawa, JP;

Junichi Mishima, Yokohama Kanagawa, JP;

Yosuke Yamahara, Kawasaki Kanagawa, JP;

Takashi Yamaguchi, Yokohama Kanagawa, JP;

Takuya Sekine, Yokohama Kanagawa, JP;

Akinori Bito, Yokohama Kanagawa, JP;

Yoshiki Yasui, Shinagawa Tokyo, JP;

Ken Okuyama, Yokohama Kanagawa, JP;

Yoshinori Shigeta, Kunitachi Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/3296 (2019.01); G06F 1/10 (2006.01); G06F 13/42 (2006.01); G06F 1/3225 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3237 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/10 (2013.01); G06F 1/3225 (2013.01); G06F 1/3237 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 13/4282 (2013.01);
Abstract

A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.


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