The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Apr. 22, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Karan Sanghi, San Jose, CA (US);

Saurabh Garg, San Jose, CA (US);

Haining Zhang, Cupertino, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 1/3293 (2019.01); G06F 1/3287 (2019.01); G06F 13/42 (2006.01); G06F 9/4401 (2018.01); G06F 1/3228 (2019.01); G06F 1/3234 (2019.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3293 (2013.01); G06F 1/3228 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/4403 (2013.01); G06F 9/4405 (2013.01); G06F 9/4411 (2013.01); G06F 11/1471 (2013.01); G06F 13/4282 (2013.01); G06F 11/1417 (2013.01); G06F 11/1474 (2013.01); G06F 2201/805 (2013.01); G06F 2201/87 (2013.01); Y02D 10/122 (2018.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01); Y02D 10/152 (2018.01); Y02D 10/171 (2018.01);
Abstract

Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a 'shared' memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.


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