The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Jul. 31, 2014
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Raghavan V. Venugopal, Spring, TX (US);

Patrick A. Raymond, Houston, TX (US);

William C. Hallowell, Spring, TX (US);

Han Wang, Sugar Land, TX (US);

Chin-Lung Chiang, Taipei, TW;

Jyun-Jie Wang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 11/14 (2006.01); G06F 11/20 (2006.01); G06F 11/30 (2006.01); G06F 1/30 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 1/263 (2013.01); G06F 1/26 (2013.01); G06F 1/305 (2013.01); G06F 11/1441 (2013.01); G06F 11/2015 (2013.01); G06F 11/3062 (2013.01); G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01);
Abstract

A test and diagnostics circuit, methods and systems are described. An example test and diagnostics circuit includes a controller and a power monitor coupled to the controller. A load switch on the test and diagnostics circuit selectably implements a load from among multiple load values to test a computing and/or data storage system. The test and diagnostics circuit includes circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the system.


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