The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Aug. 10, 2018
Applicant:

Invensense, Inc., San Jose, CA (US);

Inventors:

Michael J. Daneman, Campbell, CA (US);

Fariborz Assaderaghi, Emerald Hills, CA (US);

Assignee:

INVENSENSE, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00246 (2013.01); B81B 7/007 (2013.01); B81B 7/0025 (2013.01); B81C 1/00531 (2013.01); B81C 1/00539 (2013.01); B81C 1/00801 (2013.01); B81B 2207/015 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0133 (2013.01); B81C 2201/053 (2013.01); B81C 2203/0735 (2013.01);
Abstract

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.


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