The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Apr. 12, 2018
Applicant:

Infineon Technologies Dresden Gmbh, Dresden, DE;

Inventors:

Thoralf Kautzsch, Dresden, DE;

Steffen Bieselt, Stadt Wehlen, DE;

Heiko Froehlich, Radebeul, DE;

Andre Roeth, Dresden, DE;

Maik Stegemann, Pesterwitz, DE;

Mirko Vogt, Dresden, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B81B 7/02 (2006.01); B81B 5/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/02 (2013.01); B81B 5/00 (2013.01); B81C 1/00047 (2013.01); B81C 1/00166 (2013.01); B81C 1/00246 (2013.01); B81B 2201/0235 (2013.01); B81B 2203/033 (2013.01); B81B 2203/0315 (2013.01); B81B 2203/04 (2013.01); B81B 2203/051 (2013.01); B81B 2207/015 (2013.01); B81B 2207/095 (2013.01); B81C 2203/0714 (2013.01);
Abstract

A microelectromechanical systems (MEMS) device is provided and includes a bulk semiconductor substrate, a cavity formed in the bulk semiconductor substrate, a movably suspended mass, a cap structure and a capacitive structure is shown. The movably suspended mass is defined in the bulk semiconductor substrate by one or more trenches extending from a main surface area of the bulk semiconductor substrate to the cavity. The cap is structure arranged on the main surface area of the bulk semiconductor substrate. The capacitive structure comprises a first electrode structure arranged on the movably suspended mass and a second electrode structure arranged at the cap structure such that the first electrode structure and the second electrode structure are spaced apart in a direction perpendicular to the main surface area of the bulk semiconductor substrate.


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