The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Dec. 18, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Eung San Cho, Torrance, CA (US);

Danny Clavette, Greene, RI (US);

Darryl Galipeau, Warwick, RI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H05K 3/00 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 3/46 (2006.01); H05K 3/32 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H05K 3/0038 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H05K 1/113 (2013.01); H05K 1/142 (2013.01); H05K 1/185 (2013.01); H05K 3/0047 (2013.01); H05K 3/321 (2013.01); H05K 3/4007 (2013.01); H05K 3/4694 (2013.01); H05K 3/4602 (2013.01); H05K 2201/09536 (2013.01); H05K 2201/09563 (2013.01);
Abstract

In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.


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