The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Nov. 29, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sang-Kyeom Kim, Yongin-si, KR;

Won-Joo Yun, Yongin-si, KR;

SukYong Kang, Hwaseong-si, KR;

Ho-Jun Chang, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); G06F 1/04 (2006.01); G11C 7/22 (2006.01); H03K 5/04 (2006.01); H03K 5/156 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01); H03L 7/089 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); G11C 7/222 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); H03L 7/0812 (2013.01); H03L 7/0818 (2013.01); H03L 7/0895 (2013.01);
Abstract

A delay locked loop circuit includes a duty detector configured to detect a duty cycle of a clock signal, and to determine whether to perform a coarse duty cycle correction based on the detected duty, and a delay locked loop core. The delay locked loop core is configured to selectively perform the coarse duty cycle correction for the clock signal according to the determination of the duty detector, perform a coarse lock for the clock signal during a first time period different from a second time period in which the coarse duty cycle correction is performed, and perform a fine duty cycle correction and a fine lock for the clock signal.


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