The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Mar. 27, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Shafiullah Syed, Richardson, TX (US);

Abdellatif Bellaouar, Richardson, TX (US);

Chi Zhang, Allen, TX (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/195 (2006.01); H04B 1/04 (2006.01); H03F 3/45 (2006.01); H03F 3/217 (2006.01); H03F 1/14 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0211 (2013.01); H03F 1/0261 (2013.01); H03F 1/14 (2013.01); H03F 3/195 (2013.01); H03F 3/2171 (2013.01); H04B 1/04 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H03F 2200/451 (2013.01); H03F 2200/534 (2013.01); H03F 2200/541 (2013.01); H03F 2203/45318 (2013.01); H03F 2203/45342 (2013.01); H03F 2203/45621 (2013.01); H03F 2203/45731 (2013.01); H04B 2001/0408 (2013.01);
Abstract

An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.


Find Patent Forward Citations

Quick Actions:

Syed, Shafiullah. (2020). Method and apparatus for using back gate biasing for power amplifiers for millimeter wave devices (U.S. Patent No. 10680557). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10680557

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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