The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Dec. 02, 2016
Applicant:

Imec Vzw, Leuven, BE;

Inventor:

Hiroaki Arimura, Leuven, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/285 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/285 (2013.01); H01L 21/28255 (2013.01); H01L 21/324 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/512 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 2029/7858 (2013.01);
Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiO(x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.


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