The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2020
Filed:
Jul. 20, 2017
Applicant:
Delta Electronics, Inc., Taoyuan, TW;
Inventors:
Assignee:
DELTA ELECTRONICS, INC., Taoyuan, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 29/745 (2006.01); H01L 29/749 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7455 (2013.01); H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H01L 29/404 (2013.01); H01L 29/405 (2013.01); H01L 29/42316 (2013.01); H01L 29/66068 (2013.01); H01L 29/749 (2013.01); H01L 29/778 (2013.01);
Abstract
A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.