The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Oct. 17, 2018
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Tae Hoon Lee, Sejong-si, KR;

Jun Hee Cho, Cheongju-si, KR;

Jin Seong Chung, Cheongju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66659 (2013.01); H01L 29/0634 (2013.01); H01L 29/0847 (2013.01); H01L 29/1083 (2013.01); H01L 29/4175 (2013.01); H01L 29/7835 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.


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