The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Aug. 22, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Seung-Bum Kim, Hwaseong-si, KR;

Chan-Ho Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); H01L 27/11551 (2017.01); H01L 27/11578 (2017.01); G11C 5/02 (2006.01); G11C 29/42 (2006.01); G11C 16/34 (2006.01); G11C 29/52 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11551 (2013.01); G11C 5/025 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/10 (2013.01); G11C 16/3445 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); G11C 29/76 (2013.01); H01L 27/1157 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); G11C 29/70 (2013.01); G11C 29/88 (2013.01); G11C 2029/0411 (2013.01); G11C 2211/5621 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.


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