The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10679961 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 09, 2020

Filed:

Apr. 13, 2017
Applicant:

Tarng Yu Enterprise Co., Ltd., New Taipei, TW;

Inventors:

Tsung-Chi Chen, New Taipei, TW;

Mu-Jung Huang, New Taipei, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B23K 1/00 (2006.01); H01L 23/00 (2006.01); B23K 3/08 (2006.01); B23K 1/008 (2006.01); B23K 101/42 (2006.01);
U.S. Cl.
CPC ...
H01L 24/75 (2013.01); B23K 1/008 (2013.01); B23K 1/0016 (2013.01); B23K 3/087 (2013.01); H01L 24/81 (2013.01); B23K 2101/42 (2018.08); H01L 2224/75272 (2013.01); H01L 2224/75651 (2013.01); H01L 2224/75756 (2013.01); H01L 2224/8121 (2013.01); H01L 2224/81169 (2013.01); H01L 2924/3511 (2013.01);
Abstract

The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked package, applicable to a semiconductor package structure. A positioning rack and a plurality of conductor elements are used. A plurality of positioning holes are provided on a bottom surface of the positioning rack to form a conductor positioning area, and an operational portion is formed on an opposing surface away from the conductor positioning area, for being mounted with pick and place equipment. The conductor elements are positioned in the positioning holes. When the pick and place equipment loads and moves the positioning rack to preformed circuit contacts of the stacked package, the conductor elements are soldered to the preformed circuit contacts and then the positioning rack is removed.


Find Patent Forward Citations

Chen, Tsung-Chi. (2020). Circuit pin positioning structure, fabrication method of soldered circuit elements, and method of forming circuit pins of a stacked package (U.S. Patent No. 10679961). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10679961

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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