The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Apr. 18, 2017
Applicants:

David R. Hall, Provo, UT (US);

Marshall Soares, Taylorsville, UT (US);

Derek Maxwell, Sandy, UT (US);

Richard Rea, Lehi, UT (US);

Inventors:

David R. Hall, Provo, UT (US);

Marshall Soares, Taylorsville, UT (US);

Derek Maxwell, Sandy, UT (US);

Richard Rea, Lehi, UT (US);

Assignee:

Hall Labs LLC, Provo, UT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/29 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/18 (2006.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 21/4867 (2013.01); H01L 23/18 (2013.01); H01L 23/295 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49866 (2013.01); H01L 21/4853 (2013.01); H01L 2224/4823 (2013.01); H01L 2224/48237 (2013.01); H01L 2924/351 (2013.01);
Abstract

A heat and shock resistant integrated circuit (IC) of the present invention includes a base material, a metal layer disposed on the base material, a silicon die disposed on the metal layer, additive material disposed on the base material, gas filled filler material disposed between the additive material and the silicon die, and first traces electrically connecting the silicon die to the additive material. Packing of the integrated circuit provides exceptional thermal stress relief and impact protection of circuitry within the packaging.


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