The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Mar. 11, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Kyoung Soo Kim, Hwaseong-si, KR;

Won Young Kim, Seoul, KR;

Sun Won Kang, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); H01L 23/00 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 8/18 (2006.01); H01L 25/10 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1012 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 8/18 (2013.01); H01L 24/16 (2013.01); H01L 25/105 (2013.01); G11C 2207/105 (2013.01); G11C 2207/107 (2013.01); G11C 2207/108 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05014 (2013.01); H01L 2224/06151 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.


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