The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2020
Filed:
Jan. 20, 2017
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventors:
Sheng-Mou Lin, Hsinchu, TW;
Duen-Yi Ho, New Taipei, TW;
Assignee:
MediaTek Inc., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/49838 (2013.01); H01L 23/5286 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3025 (2013.01);
Abstract
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.