The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

Apr. 30, 2019
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Jainendra Singh, Bangalore, IN;

Jwalant Kumar Mishra, Bangalore, IN;

Patrick Van de Steeg, Oss, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 17/08 (2006.01); G11C 11/412 (2006.01); G11C 11/417 (2006.01);
U.S. Cl.
CPC ...
G11C 17/08 (2013.01); G11C 8/08 (2013.01); G11C 11/412 (2013.01); G11C 11/417 (2013.01);
Abstract

A read-only memory (ROM) includes ROM cells and a bias control circuit for biasing the ROM cells. Each ROM cell includes a set of transistors. The bias control circuit is connected to body terminals of the transistors of each ROM cell to provide a bias voltage. The bias voltage, which is temperature-dependent, is generated based on junction leakages at the body terminals of the transistors. The bias control circuit controls threshold voltages of the transistors using the bias voltage. The use of a temperature-dependent bias voltage to bias the body terminals of the transistors allows for a relatively constant read margin for each ROM cell.


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