The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

May. 22, 2019
Applicant:

AU Optronics Corporation, Hsin-Chu, TW;

Inventors:

Shao-Ting Chen, Hsin-Chu, TW;

Yi-Fan Lin, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); H03K 17/693 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); H03K 3/037 (2013.01); H03K 17/693 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0297 (2013.01);
Abstract

A display panel includes a plurality of data lines and a multiplexer circuit including a first switch set and a second switch set each having a plurality of switches. Each switch of the switch sets has a first end connected to the data lines and a second end. The second ends of a same switch set are connected to each other to form a receiving end connected to a data signal source. The first switch set is turned on alternately by a first clock signal and a second clock signal. The second switch set is turned alternately by a third clock signal and a fourth clock signal. The enabling period of the first clock signal and that of the third clock signal partially overlap and have asynchronous starting times. The enabling period of the second clock signal and that of the fourth clock signal at least partially overlap.


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