Space exploration with bayesian inference

Abstract

A system, a computer program product, and method for physically fabricating an electronic circuit using design space exploration as part of a design process is described. The method begins with defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters. Next an output target to be optimized is defined. A series of one or more test mask shapes are generated to appear on a photo mask using the plurality of design space parameters. A simulation of a post lithography or etch on the series of one or more test mask shapes is performed to produce simulation output values. Next, the simulation output values and corresponding design space parameters are fed into to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate.