The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2020

Filed:

May. 14, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Yukie Suzuki, Atsugi, JP;

Hideaki Kuwabara, Isehara, JP;

Hajime Kimura, Atsugi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); G02F 1/1339 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/1339 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 27/1214 (2013.01); H01L 27/1222 (2013.01); H01L 27/1288 (2013.01); H01L 29/04 (2013.01); H01L 29/66765 (2013.01); H01L 29/78678 (2013.01); H01L 29/78696 (2013.01); H01L 29/458 (2013.01); H01L 29/4908 (2013.01);
Abstract

A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.


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