The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Jan. 09, 2018
Applicant:

A.t.e. Solutions, Inc., El Segundo, CA (US);

Inventors:

Louis Yehuda Ungar, Playa del Rey, CA (US);

Tak Ming Mak, Union City, CA (US);

Neil Glenn Jacobson, Los Altos, CA (US);

Assignee:

A.T.E. SOLUTIONS, INC., El Segundo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H04L 12/26 (2006.01); G01R 31/319 (2006.01); G06F 11/263 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
H04L 43/087 (2013.01); G01R 31/31905 (2013.01); G01R 31/31908 (2013.01); G06F 11/221 (2013.01); G06F 11/263 (2013.01); H04L 43/50 (2013.01); H04L 43/0847 (2013.01); H04L 43/14 (2013.01);
Abstract

A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.


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