The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Dec. 19, 2012
Applicant:

Valeo Systemes DE Contrôle Moteur, Cergy St Christophe, FR;

Inventors:

Valéry Becquet, Molliens-Dreuil, FR;

Olivier Garot, Vaureal, FR;

Assignee:

Valeo Systemes de Controle Moteur, Cergy Saint Christophe, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 15/00 (2006.01); G06F 13/42 (2006.01); H04L 5/14 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H04B 15/00 (2013.01); G06F 13/4282 (2013.01); G06F 13/4291 (2013.01); H04L 5/14 (2013.01); H04L 5/1469 (2013.01); H04L 25/0266 (2013.01); H04L 25/0272 (2013.01);
Abstract

The invention relates to a method for communicating between at least one first system () and at least one second system () via a full-duplex synchronous serial link () capable of simultaneously routing data between said systems (), said data comprising: at least one message () from the first system () to the second system (), at least one message () from the second system () to the first system (), and a clock signal (). According to the method: the second system () receives a message () and a clock signal () sent by the first system (), delayed and substantially in phase; the second system () sends the first system () a message (); the clock signal () received by the second system () is returned () to the first system () along with the message () sent by the second system (); and the first system () receives the message () sent by the second system () and the returned clock signal (), delayed and substantially in phase.


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