The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Aug. 12, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Bharat Gajanan Hegde, Sirsi, IN;

Devraj Matharampallil Rajagopal, Bangalore, IN;

Srikanth Srinivasan, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/007 (2006.01); H03K 17/0814 (2006.01); H03K 3/3562 (2006.01); H03K 19/17788 (2020.01);
U.S. Cl.
CPC ...
H03K 19/007 (2013.01); H03K 3/35625 (2013.01); H03K 17/08142 (2013.01); H03K 19/17788 (2013.01);
Abstract

A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.


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