The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2020
Filed:
May. 16, 2018
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;
Inventors:
Hyun Lee, Gyeyang-gu Incheon, KR;
Dae Seong Lee, Busan, KR;
Minsu Kim, Hwaseong-si, KR;
Ahreum Kim, Daegu, KR;
Chunghee Kim, Yongin-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H03K 19/20 (2006.01); G06F 1/10 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); G01R 31/3177 (2013.01); G01R 31/31727 (2013.01); G06F 1/10 (2013.01); H03K 19/20 (2013.01);
Abstract
An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.