The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Jan. 24, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xinmin Yu, San Diego, CA (US);

Lai Kan Leung, San Marcos, CA (US);

Yunfei Feng, San Diego, CA (US);

Chirag Dipak Patel, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/04 (2006.01); H03D 7/14 (2006.01); H04B 1/40 (2015.01); H04B 1/28 (2006.01); H04B 1/00 (2006.01); H04B 1/16 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H03H 11/0422 (2013.01); H03D 7/1441 (2013.01); H03D 7/1458 (2013.01); H04B 1/0096 (2013.01); H04B 1/16 (2013.01); H04B 1/28 (2013.01); H04B 1/40 (2013.01); H03D 2200/0023 (2013.01); H03D 2200/0043 (2013.01); H03D 2200/0088 (2013.01); H04B 2001/0491 (2013.01);
Abstract

The present disclosure provides an apparatus that includes a first mixer circuit configured to convert between an RF signal and an IF signal based at least in part on an local oscillator (LO) signal. The first mixer circuit is electrically coupled to a first node that is configured to receive the LO signal and a first bias voltage, a second node that is configured to receive the RF signal or the IF signal, and a third node that is configured to provide the IF signal or the RF signal. The apparatus further includes a second mixer circuit electrically coupled to a fourth node configured to receive the LO signal and a second bias voltage, the second node, and the third node. The second bias voltage has a voltage level that is offset from the first bias voltage.


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