The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Aug. 28, 2018
Applicant:

Nichia Corporation, Anan-shi, Tokushima, JP;

Inventor:

Hirofumi Kawaguchi, Tokushima, JP;

Assignee:

NICHIA CORPORATION, Anan-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/38 (2010.01); H01L 33/62 (2010.01); H01L 33/42 (2010.01); H01L 21/786 (2006.01); H01L 33/40 (2010.01); H01L 33/32 (2010.01);
U.S. Cl.
CPC ...
H01L 33/007 (2013.01); H01L 21/786 (2013.01); H01L 33/0079 (2013.01); H01L 33/32 (2013.01); H01L 33/38 (2013.01); H01L 33/405 (2013.01); H01L 33/42 (2013.01); H01L 33/62 (2013.01); H01L 33/325 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A method of manufacturing a light emitting device includes: a first wafer preparation step including preparing, on a first substrate, m first wafers (where m≥2), each of the first wafers comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a second wafer preparation step including bonding a second substrate with the second semiconductor layer of a first of the m first wafers and then removing the first substrate from the first wafer, so as to form a second wafer in which the first semiconductor layer is exposed; and a first bonding step including bonding the first semiconductor layer exposed at the surface of the second wafer and the second semiconductor layer of a second of the m first wafers together using a light-transmissive conductive layer, and then removing a first substrate of the second of the m first wafers.


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