The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Jul. 04, 2019
Applicant:

AU Optronics Corporation, Hsinchu, TW;

Inventors:

Ming-Yan Chen, Hsinchu County, TW;

Ming-Hsien Lee, Hsinchu, TW;

Che-Chia Chang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7836 (2013.01); H01L 29/42376 (2013.01); H01L 29/45 (2013.01); H01L 29/513 (2013.01); H01L 29/7831 (2013.01);
Abstract

A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.


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