The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Dec. 11, 2018
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Jan Van Houdt, Bekkevoort, BE;

Hanns Christoph Adelmann, Wilsele, BE;

Han Chung Lin, Heverlee, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6684 (2013.01); H01L 21/02356 (2013.01); H01L 29/1606 (2013.01); H01L 29/516 (2013.01); H01L 29/66045 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66969 (2013.01); H01L 29/78391 (2014.09);
Abstract

The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.


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