Silicide block isolation for reducing off-capacitance of a radio frequency (rf) switch

Abstract

A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions.