The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Feb. 05, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Hiroki Tokuhira, Kawasaki Kanagawa, JP;

Kazuhiko Yamamoto, Fujisawa Kanagawa, JP;

Kunifumi Suzuki, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

A semiconductor memory device includes a stacked body including insulating layers and gate electrode layers alternately stacked in a direction, a semiconductor layer extending in the direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, and including a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer includes a first insulator, the second layer includes at least one oxide selected from aluminum oxide, yttrium oxide, lanthanum oxide, gadolinium oxide, ytterbium oxide, hafnium oxide, and zirconium oxide, the third layer includes at least one material selected from silicon, germanium, silicon germanium and silicon carbide, and the third layer is positioned between the semiconductor layer and the insulating layer.


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