The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2020
Filed:
Oct. 31, 2018
Infineon Technologies Ag, Neubiberg, DE;
Markus Zundel, Egmating, DE;
Stefan Mieslinger, Kottgeisering, DE;
Thomas Ostermann, Koestenburg, AT;
Christian Westermeier, Munich, DE;
Jochen Hilsenbeck, Villach, AT;
Jens Peter Konrath, Villach, AT;
Boris Mayerhofer, Neubiberg, DE;
Anatoly Sotnikov, Neubiberg, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.