The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2020
Filed:
Sep. 24, 2019
The Penn State Research Foundation, University Park, PA (US);
Xueqing Li, State College, PA (US);
Sumitha George, State College, PA (US);
John Sampson, State College, PA (US);
Sumeet Gupta, State College, PA (US);
Suman Datta, South Bend, IN (US);
Vijaykrishnan Narayanan, State College, PA (US);
Kaisheng Ma, State College, PA (US);
The Penn State Research Foundation, University Park, PA (US);
Abstract
Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I−Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.