The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Nov. 06, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong-Hun Kwak, Hwaseong-si, KR;

Hee-Woong Kang, Suwon-si, KR;

Jun-Ho Seo, Hwaseong-si, KR;

Hee-Won Lee, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4074 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01); G11C 16/08 (2006.01); G11C 11/408 (2006.01); G11C 11/4097 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 7/109 (2013.01); G11C 7/12 (2013.01); G11C 8/12 (2013.01); G11C 11/4082 (2013.01); G11C 11/4085 (2013.01); G11C 11/4097 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 16/3436 (2013.01); G11C 2207/2209 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.


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