The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Jul. 11, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Seong Il O, Suwon-si, KR;

Jun Hyung Kim, Suwon-si, KR;

Kyo Min Sohn, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); G11C 8/18 (2006.01); G11C 8/12 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G11C 29/18 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/062 (2013.01); G11C 7/065 (2013.01); G11C 7/106 (2013.01); G11C 7/1006 (2013.01); G11C 7/1045 (2013.01); G11C 8/12 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 29/18 (2013.01); G11C 2207/2272 (2013.01);
Abstract

A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.


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