The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Mar. 19, 2019
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventor:

Steven E. Finn, Chamblee, GA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); H03D 3/00 (2006.01); H03G 3/30 (2006.01); H03K 5/1536 (2006.01); H04L 27/156 (2006.01); H04L 25/06 (2006.01); G11C 7/22 (2006.01); H03G 1/00 (2006.01); H03G 1/04 (2006.01); H04L 1/20 (2006.01); H04L 25/03 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1066 (2013.01); G11C 7/22 (2013.01); H03D 3/008 (2013.01); H03G 1/0029 (2013.01); H03G 1/04 (2013.01); H03G 3/3052 (2013.01); H03K 5/1536 (2013.01); H04L 1/20 (2013.01); H04L 25/03885 (2013.01); H04L 25/069 (2013.01); H04L 27/1563 (2013.01);
Abstract

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.


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