The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Nov. 08, 2017
Applicant:

Samsung Display Co., Ltd., Yongin-Si, Gyeonggi-Do, KR;

Inventors:

Min-Soo Choi, Hwaseong-si, KR;

Junpyo Lee, Asan-si, KR;

Yu-Chol Kim, Pyeongtaek-si, KR;

Jeong-Hyun Kim, Seongnam-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/10 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 3/2003 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0871 (2013.01); G09G 2310/0213 (2013.01); G09G 2310/0218 (2013.01); G09G 2310/0235 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01);
Abstract

A display apparatus includes a gate driving control circuit, a gate driver and a display panel. The gate driving control circuit generates N gate clock signals and N inversion gate clock signals based on N gate clock control signals, phases of which partially overlap with each other. Each inversion gate clock signals has an opposite phase to a respective gate clock signal. The gate driver generates gate signals based on the N gate clock signals or the N inversion gate clock signals and applies the gate signals to gate lines. The display panel includes pixels, each connected to a respective gate line and a respective data line. Each of the pixels has a longer side in parallel with gate lines and a shorter side in parallel with the data lines. A number of the gate clock control signals is an integer multiple of a number of colors of the pixels.


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