The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2020
Filed:
Sep. 09, 2019
Efabless Corporation, San Jose, CA (US);
Bertrand Irissou, San Jose, CA (US);
John M. Hughes, Hartford, CT (US);
Lucio Lanza, Palo Alto, CA (US);
Mohamed K. Kassem, Carlsbad, CA (US);
Michael S. Wishart, Hillsborough, CA (US);
Rajeev Srivastava, Austin, TX (US);
Risto Bell, San Jose, CA (US);
Robert Timothy Edwards, Poolesville, MD (US);
Sherif Eid, Sunnyvale, CA (US);
Greg P. Shaurette, Tahoe City, CA (US);
efavless corporation, San Jose, CA (US);
Abstract
Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.