The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Dec. 20, 2016
Applicant:

Ab Initio Technology Llc, Lexington, MA (US);

Inventors:

Victor T. Abaya, Bedford, MA (US);

Russell L. Bryan, Bedford, MA (US);

Brond Larson, Sharon, MA (US);

Carl Offner, Sudbury, MA (US);

Daniel J. Teven, Sharon, MA (US);

Assignee:

Ab Initio Technology LLC, Lexington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/901 (2019.01); G06F 3/0481 (2013.01); G06F 3/0484 (2013.01); G06F 16/22 (2019.01); G06F 16/21 (2019.01); G06F 8/34 (2018.01);
U.S. Cl.
CPC ...
G06F 16/9024 (2019.01); G06F 3/0481 (2013.01); G06F 3/04847 (2013.01); G06F 8/34 (2013.01); G06F 16/211 (2019.01); G06F 16/22 (2019.01);
Abstract

A specification including a description of a first directed graph including a first plurality of components interconnected by a first set of one or more directed links is received. A graph interface is formed for the first plurality of components including: forming a first interface element of the graph interface, the first interface element being associated with a first port of a first component of the first number of components, and configuring one or more properties of the first interface element such that the first port of the first component is consistent with the one or more properties of the first interface element. A first implementation of the graph interface is formed including the first number of components, the forming including forming a first correspondence between the first interface element and the first port of the first component of the first number of components.


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