The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2020
Filed:
Aug. 16, 2019
Applicant:
Ambarella International Lp, Santa Clara, CA (US);
Inventors:
Leslie D. Kohn, Saratoga, CA (US);
Robert C. Kunz, Sunnyvale, CA (US);
Assignee:
Ambarella International LP, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 3/061 (2013.01); G06F 3/0625 (2013.01); G06F 3/0631 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 9/30036 (2013.01); G06F 9/3877 (2013.01); G06F 9/3887 (2013.01); G06F 13/28 (2013.01);
Abstract
An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.