The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Feb. 15, 2018
Applicant:

Azul Systems, Inc., Sunnyvale, CA (US);

Inventors:

Gil Tene, Los Altos Hills, CA (US);

Michael A. Wolf, San Francisco, CA (US);

Cliff N. Click, Jr., San Jose, CA (US);

Assignee:

Azul Systems, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 11/36 (2006.01); G06F 9/30 (2018.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3842 (2013.01); G06F 9/30076 (2013.01); G06F 9/3834 (2013.01); G06F 9/3851 (2013.01); G06F 9/52 (2013.01); G06F 11/3636 (2013.01);
Abstract

A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.


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