The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Sep. 20, 2017
Applicant:

Tesla, Inc., Palo Alto, CA (US);

Inventors:

Peter Joseph Bannon, Woodside, CA (US);

Kevin Altair Hurd, Redwood City, CA (US);

Emil Talpes, San Mateo, CA (US);

Assignee:

Tesla, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); G06F 7/575 (2006.01); G06T 1/20 (2006.01); G06F 15/80 (2006.01); G06F 7/52 (2006.01); G06F 7/50 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); G06F 7/544 (2006.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 7/575 (2013.01); G06F 7/50 (2013.01); G06F 7/52 (2013.01); G06F 7/5443 (2013.01); G06F 15/80 (2013.01); G06F 17/16 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06T 1/20 (2013.01);
Abstract

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.


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