The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2020

Filed:

Dec. 31, 2018
Applicant:

Nanjing Iluvatar Corex Technology Co., Ltd., Nanjing, CN;

Inventors:

Pingping Shao, San Jose, CA (US);

Jiejun Chen, Shanghai, CN;

Yongliu Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G06N 5/02 (2006.01); H03M 7/30 (2006.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0608 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 12/0802 (2013.01); G06N 5/02 (2013.01); H03M 7/3066 (2013.01); G06F 12/0811 (2013.01); G06N 5/022 (2013.01);
Abstract

A hierarchical sparse tensor compression method based on artificial intelligence devices, in DRAM, not only saves the storage space of the neuron surface, but also adds a meta-surface to the mask block. When reading data, the mask is first read, then the size of the non-zero data is calculated, and only these non-zero data are read to save DRAM bandwidth. In the cache, only non-zero data is stored, so the required storage space is reduced. When processing data, only non-zero data is used. The method uses a bit mask to determine if the data is zero. There are three levels in the hierarchical compression scheme: tiles, lines, and points, reading bitmasks and non-zero data from DRAM, and saving bandwidth by not reading zero data. When processing data, if their bit mask is zero, the tile data may be easily removed.


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