The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Sep. 26, 2018
Applicant:

United States of America As Represented BY the Administrator of Nasa, Washington, DC (US);

Inventors:

David J. Petrick, Severna Park, MD (US);

Alessandro D. Geist, Bethesda, MD (US);

Thomas P. Flatley, Huntington, MD (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/18 (2006.01); H03K 19/003 (2006.01); H05K 1/11 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H03K 19/0033 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); G06F 11/0727 (2013.01); G06F 11/0793 (2013.01); H05K 1/0203 (2013.01); H05K 2201/093 (2013.01); H05K 2201/09327 (2013.01); H05K 2201/09509 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10212 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10545 (2013.01);
Abstract

The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.


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