The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Feb. 27, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Matthew John Ascher Schurmann, Manchester, NH (US);

Mayank Jain, Bengaluru, IN;

Wenkai Wu, East Greenwich, RI (US);

Preetam Charan Anand Tadeparthy, Bangalore, IN;

Kuang-Yao Cheng, Bedford, NH (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/10 (2006.01); H03M 1/16 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1023 (2013.01); H03K 19/1733 (2013.01); H03M 1/1057 (2013.01); H03M 1/162 (2013.01);
Abstract

A circuit includes a phase control logic, an analog-to-digital converter (ADC), and digital logic. The phase control logic is configured to couple to a plurality of power phases of a multi-phase power supply. The digital logic is configured to couple to the phase control logic and the ADC, to receive an instruction to operate in a self-calibration mode of operation, receive a first message including a value associated with a calibrated load configured to couple to the plurality of power phases, perform a self-calibration sub-routine for each power phase of the plurality of power phases based at least partially on the received instruction, the received first message, and a signal received from the ADC, and receive a second message instructing the digital logic to store a result of the self-calibration in a memory of the circuit.


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