The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2020
Filed:
Jul. 03, 2019
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Srikanth Srinivasan, Bengaluru, IN;
Devraj Rajagopal, Bengaluru, IN;
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/007 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/007 (2013.01); H03K 19/018521 (2013.01);
Abstract
A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.
Quick Actions:
Srinivasan, Srikanth. (2020). Failsafe, ultra-wide voltage input output interface using low-voltage gate oxide transistors (U.S. Patent No. 10666257). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10666257
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile