The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Nov. 07, 2018
Applicant:

Epistar Corporation, Hsinchu, TW;

Inventors:

Jing-Jie Dai, Hsinchu, TW;

Tzu-Chieh Hu, Hsinchu, TW;

Assignee:

Epistar Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/14 (2010.01); H01L 33/32 (2010.01); H01L 33/06 (2010.01); H01L 33/30 (2010.01); H01L 33/00 (2010.01); H01L 33/04 (2010.01);
U.S. Cl.
CPC ...
H01L 33/145 (2013.01); H01L 33/0062 (2013.01); H01L 33/04 (2013.01); H01L 33/06 (2013.01); H01L 33/14 (2013.01); H01L 33/30 (2013.01); H01L 33/305 (2013.01); H01L 33/32 (2013.01); H01L 33/325 (2013.01);
Abstract

A semiconductor device includes: a first semiconductor layer; a second semiconductor layer including a first dopant of a first conductivity type and a second dopant of a second conductivity type, wherein the first dopant has a doping concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer includes a third dopant including a doping concentration higher than the doping concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer includes a bottom surface facing the active region, and the active region includes a top surface facing the second semiconductor layer, and a distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.


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