The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Jul. 30, 2019
Applicant:

AU Optronics Corporation, Hsinchu, TW;

Inventors:

Cheng-Kuang Wang, Hsinchu County, TW;

Chun-Da Tu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G11C 19/28 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G09G 3/20 (2013.01); G11C 19/28 (2013.01); H01L 27/1255 (2013.01); G09G 3/2092 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A display panel including a display region and a non-display region, a plurality of gate lines, a plurality of data lines, a pixel array and a gate on array circuit. The non-display region is located at one side of the display region. The plurality of gate lines and the plurality of data lines are disposed in the display region. The pixel array is located in the display region, wherein the pixel array is composed of a plurality of pixel units that are repeatedly arranged. The pixel units consist of three gate lines, two data lines and six sub-pixels, and each sub-pixel is electrically connected to one of the gate lines and one of the data lines located in the pixel array respectively. The gate on array circuit is disposed in the pixel array.


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